1. Field of the Invention
The present invention relates to a semiconductor memory device having P channel type MOS transistors, and particularly relates to a semiconductor memory device in which many sub-word drivers corresponding to a hierarchical word line structure are constituted by the P channel type MOS transistors.
2. Description of the Related Art
In a field of a DRAM (Dynamic Random Access Memory) serving as a large-capacity semiconductor memory device, suppressing leak current of a transistor has been demanded in accordance with miniaturization of process and lower voltage in recent years. Particularly, suppressing GIDL (Gate Induced Drain Leakage) current, which is included in the leak current, flowing through a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) has been a problem.
FIG. 7 illustrates a state where the GIDL current occurs in a PMOS transistor. In FIG. 7, a cross-sectional structure corresponding to the PMOS transistor formed on a semiconductor substrate is shown, in which an N-well 100, a diffusion region 101 applied with a boost voltage VPP, a diffusion region 102 applied with a ground potential VSS, and a diffusion region 103 applied with a negative potential VKK are formed. Also, a gate electrode 105 applied with the boost voltage VPP is formed on between a drain and a source via a gate oxide film 104.
The N-well 100 is biased by the boost voltage VPP via the diffusion region 101, and the PMOS transistor is brought into an OFF state due to a potential relationship between the diffusion regions 102 and 103 and the gate electrode 105. On the other hand, if a depletion layer extends in a PN junction around the diffusion regions 102 and 103, an effect of impurity concentration causes GIDL current as the leak current to flow (arrows indicate the direction of electrons) near the surface of the depletion layer. The magnitude of the GIDL current changes exponentially relative to an electric field E generated at the gate oxide film 104, on the basis of the boost voltage VPP. In order to suppress the GIDL current, the electric field E needs to be reduced, and it is desirable to sufficiently reduce the boost voltage VPP for that purpose.
A typical DRAM includes many PMOS transistors each having the structure shown in FIG. 7. Particularly, in a DRAM having a hierarchical word line structure, many PMOS transistors are used in a sub-word driver for activating a sub-word line corresponding to a main word line (e.g., see Japanese Unexamined Patent Application Publication No. 2005-135461). In a large-capacity DRAM, the sum of GIDL currents flowing through the PMOS transistors of all sub-word drivers is too large to ignore. Particularly, in a mobile DRAM, the current needs to be sufficiently small in a standby state and thus the GIDL current needs to be adequately suppressed.
In the structure of the typical DRAM, the gate of each PMOS transistor of the sub-word driver is directly connected to a main word driver. On the other hand, as described above, it is difficult to suppress the boost voltage VPP such that the GIDL current can be ignored, due to restrictions of a circuit operation of the main word driver. Typically, when the main word line is in an inactive state, the boot voltage VPP is applied to gates of the PMOS transistors to bring them into an OFF state and thus the above-described effect of the GIDL current is inevitable. Particularly, in the mobile DRAM, it is a problem that the GIDL current accounts for a large proportion of the current flowing in the standby state, which hinders low-current operation. In FIG. 7, if a strong electric field E occurs at the gate oxide film 104 of the PMOS transistor, a decrease in reliability of the gate oxide film 104 is also a problem.